The present invention is directed, in general, to semiconductor manufacturing and, more specifically, to a method for concurrently forming electrostatic discharge protection devices and shallow trench isolation regions.
The continued drive toward decreased feature size in semiconductor devices to improve device performance has made the devices increasingly vulnerable to electrostatic discharge (ESD) damage. ESD can be triggered in a semiconductor device by any unforeseen build up of electrostatic charge in the semiconductor device. While ESD may occur in any part of a semiconductor device, the device can readily be damaged by a voltage surge that is introduced into the device via a bond pad. This voltage surge can be induced by direct contact with surrounding equipment to which the bond pad is connected, or by human contact. To prevent this kind of damage, an ESD protection circuit comprising at least a resistor and a capacitor is typically included in the design of the semiconductor device. The essential function of ESD protection is to direct the ESD current away from the semiconductor circuits that the ESD circuit is designed to protect. ESD circuits are used to protect memory circuits, MOSFET""s and other semiconductor device applications for the protection of input/output buffers.
Protective ESD circuits are typically located between the input and output pads on the die and the transistor gates to which the pads are electrically connected. A 150 ns decaying pulse can be obtained with a 100 pf capacitor discharging into a 1.5 kxcexa9 resistor and then into the integrated circuit. Conventional ESD capacitors are formed as layers, i.e., a gate over a thin oxide over a substrate, wherein the thin oxide functions as the dielectric. Such capacitors may require relatively large areas to provide the required capacitance. Thus, conventional ESD circuits are constrained in size by the capacitor. With the continued emphasis on making integrated circuits ever smaller, it is highly desirable to be able to reduce the footprint of the ESD capacitor.
Accordingly, what is needed in the art is a method of forming an ESD capacitor that overcomes the deficiencies associated with conventional ESD capacitors.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. In one embodiment the invention comprises concurrently forming, in a conductive substrate, an isolation trench and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.